2. The figure Fig.22 presents a design that integrates 5 IP blocks with the propagation delays as shown inside the blocks. 5 15 ns 5 5 ns ns 10 ns 5 ns Fig.22. a) Calculate the maximum frequency the design can run at as itis, (4 marks) b) Pipeline the design into two parts by inserting extra register(s) where appropriate on the block diagram. Try achieving as high operating frequency as possible by balancing stages of the pipeline. Calculate the maximum frequency the pipelined design can run at (11 marks)