[20/20/20/20] The spin lock is the simplest synchronization mechanism possible on most commercial shared-memory machines. This spin lock relies on the exchange primitive to atomically load the old value and store a new value. The lock routine performs the exchange operation repeatedly unt it finds the lock unlocked (i.e., the returned value is 0). add i x2, x0, #1 lockit: EXCH x2. 0 (x1) bnez x2. lockit The lock is released simply by storing a 0 into x2 As discussed in Section 5.5, the more optimized spin lock employs cache coherence and uses a load to check the lock, allowing it to spin with a shared var iable in the cache. lockit: 1d bnez addi EXCH bnez x2, 0 (x1) x2. lockit x2, x0, #1 x2.0(x1) x2. lockit Assume that processor cores CO, CI, and C3 are all trying to acquire a lock at address 0xAC00 (i.e., register R1 holds the value 0xACOO). Assume the cache con- tents from Figure 5.37 and the timing parameters from Implementation in Figure 5.38. For simplicity, assume the critical sections are 1000 cycles long. a. [20] Using the simple spin lock, determine approximately how many ncurs be memory stall cycles each processor i memory stall cycles each processor incurs before acquiring the lock accesses occur? fore acquiring the lock. b. [201 Using the optimized spin lock, determine approximately how many c. 120] Using the simple spin lock, approximately how many memory d. [20] Using the optimized spin lock, approximately how many memory accesses occur? Core Figure 5.37 Multicore (point-to-point) multiprocessor Implementation 1 Cycles 100 40 Implementation 2 Cycles 100 130 Parameter N, Nwritebsack Figure 5.38 Snooping coherence latencies