2.15 A rate. a) True b) False 2.16 Which of the following statements about pipelining a processor is correct? Compared to a single cycle processor, a pipelined processor has the same average CPI. (ii) Compared to a single cycle processor, pipelining can usually increase clock frequency (i) Write-ofer-write (WAW) data hazard cannot happen in the 5-stage pipeline processor o) only b) () and (i) only ) () and (ii) only d (ii) and ii) only f 1 to 2.17 Let Assume you break up the memory stage into 2 stages instead o improve throughput in a pipelined. Thus, the pipeline stages ar e now: IF, ID, EX, M1, M2, WHB How many clock cycles it will take the instructions though this 6 stage pipeline. below would progress lw $5, 0(S4) add $7, $5, $5 sub $8, $5, $9 Like before, full forwarding hardware is available. a) 6 b) 10 c) 12 d) 14 ier he any control hazard in a single-cycle processor