2.2. Project 2: Influence of the Cache Size Purpose Show the influence of the cache size on the miss rate. Development Configure a system with the following architectural characteristics: Processors in SMP = 1. Cache coherence protocol = MESI. Scheme for bus arbitration = Random. Word wide (bits) = 16. Words by block = 16 (block size = 32 bytes). Blocks in main memory = 8192 (main memory size = 256 KB). Mapping = Fully-Associative. Replacement policy = LRU. Configure the blocks in cache using the following configurations: 1 (cache size = 0,03 KB), 2, 4, 8, 16, 32, 64, 128, 256, and 512 (cache size = 16 KB). For each of the configurations, obtain the miss rate using the trace files (extension .prg): Hydro, Nasa7, Cexp, Mdljd, Ear, Comp, Wave, Swm and UComp. Does the miss rate increase or decrease as the cache size increases? Why?