2.4 Assignment Overview In this assignment you will use Vivado 2017.2 Webpack to write and simulate some simple VHDL files There are two main tasks in this assignment. The first being a Full-Adder circuit and the second being a slightly more complicated circuit that you will simplify from a given equation. Using the techniques learned in class and from the tutorial, complete both tasks. You'll also need to turn in a single PDF to Canvas (instructions at the end of the file) Getting started 1. Create a directory to store all of the assignment's files. 2. Open Vivado 2017.2 and create a new project called computer_assignment_1 3. It will be an RTL project . No sources to input. Although if the target and simulation languages aren't set to vhdl, change 5. 6. 7. them to vhdl No existing IP No constraints file The Basys3 uses an XC7A35T-CPG236C FPGA o Artix family O Speed grade -1 o CPG236 packaging o 41600 FlipFlops Task 1 This task is to implement the function Sum-ABBc and CoutAB+BC+AC in task1.vhd. It may seem trivial but it's a good starting point. Make sure to read the instructions before starting 1. Add the task1.vhd file: a. b. C. Under "Flow Navigator" click Add sources." Select "Create or add design sources." Add task!.vhd and then click Finish." 2. Once you have your VHDL source file, edit it to implement the function