2.8[10] Translate the following RISC-V code to C. Assume that the variables t,,,1, and 1 are assigned to registers 5,6,7,27, and x29, respectively. Assume that the base address of the arrays A and E are in registers 10 and x12, respectively. add730,10,0addx31,x10,0nd332,6(x20)id330,0(x30)add5,30,x.13 2.9[20]&582.2,2.5> For each RISC-V instruction in Exercise 2.8, show the value of the opcode (op), source register (rs1), and destination register (rd) fields. For the I-type instructions, show the value of the immediate field, and for the R-type instructions, show the value of the second source register (rs2). For non U- and 359 UJ-type instructions, show the funct 3 field, and for R-type and S type instructions, also show the funct7 field. 2.12[5] Provide the instruction type and assembly language instruction for the following binary value: 00000000000100001000000010110011 tw