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2a) (5pts) Provide a diagram for a single-bit memory constructed from a multiplexor. 2b) (5pts) Provide a diagram for a single-bit JK memory edge-triggered flip-flop

2a) (5pts) Provide a diagram for a single-bit memory constructed from a multiplexor.

2b) (5pts) Provide a diagram for a single-bit JK memory edge-triggered flip-flop

2c) (10pts) Provide a diagram for a multiplexor/demultiplexor pair, with four inputs and outputs, and control lines as needed. Use two-input gates in positive logic.

please help me with this question

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