$(30$pt$)$ The following figure shows single cycle implementation for datapath and control path for MIPS architecture.

Fill $0,1$ or $x($don$\text{'}$t care$)$ in the following table to implement for the architecture.

$\backslash$table$[[$Instruction$,\backslash$table$[[$ALU$],[$Sre$]],\backslash$table$[[$MEMt$],[$oReg$]],\backslash$table$[[$Reg$],[$Write$]],\backslash$table$[[$Mem$],[$Read$]],\backslash$table$[[$Mem$],[$Write$]],\backslash$table$[[$Bra$],[$nch$]]],[\backslash$table$[[$R$-$type$],[$instruction$]],1)0,(2)0,(3)||,(4)0,(5)0,(6)0],[$Load$,(7)1,(8)1,(9)$ I,$(10)$ I,$(11)0,(12)0],[$Store$,(13)$ I,$(14)0,(15)0,(16)0,(17)|,(18)0],[$b$($branch$),(19)0,(20)0,(21)0,(22)0,(24)0,(24)],[$addi$,(25)1,(26)0,(27)|,(28)0,(29)0,(30)0$