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3. (10 pts) Briefly answer the following questions a. (lpts) What is CPI? What does it mean if we have high CPI (assuming others are

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3. (10 pts) Briefly answer the following questions a. (lpts) What is CPI? What does it mean if we have high CPI (assuming others are the same), i.e. better or (Ipts) You are inventing your own ISA. You decide all instructions should have the same length and b. enco ding tormat. Assume that all your instructions use MIPS's l-type encoding format. What is the maximum number of different instructions of your ISA? Why? c (pts) Why lw and sw are encoded using I-format instead of R-format?i.e, what is the benefit? d. (5pts) Mark each question as True/False (T/F) A I 6-bit immediate value can be assigned to the register hi using a MIPS instruction. The "jump" operation of a branch/jump instruction is completed by changing the value of PC. In MIPS, you cannot use a single instruction to add a register and a memory operand. A 32-bit value in memory can be loaded into a register by a single MIPS instruction. In MIPS, each memory location is a word (32-bit). After executing the instruction: lw $t5, 4(Sa0), the value of Sts is equal to Sa0+4 A computer consists of the following three major components: CPU, memory, input/output. SPEC benchmarks are always used for computer performance evaluation in computer industry. A 8kB memory requires 13 bits of address. According to memory alignment requirement, memory address must be a multiple of data size. So the instruction sw Ss5, 3(Sal) is invalid since the offset is not a multiple of 4. e. (2pts) Circle the features that belong to CISC (a) Variable-length instructions (c) Many addressing modes (e) Smaller CPI (g) Fast decoding of instructions.(h) T (b) Only load-store access memory (d) Fewer operations (f) Smaller instruction count Two-address architecture 4. (10pts) Follow the instructions below CONSECUTIVELY, and write the value of destination register in decimal into the space provided. If the instruction is not ex ecuted, put the symbol " ? in the provide s pace. ori sso, $zero, 15 addi Ss1.Sso,-11 sll Ss2, Ss1,4 siti Ss3, Ss2, 60 beq Ss3, Szero, L1 and Ss4, Ss3, Ss1 j L2 #Sso " #Ssl # Ss2- #SS3- #5s4= L1: sub Ss5, Ss3, Ss1 L2: #55

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