$[32$ points$]$

The block diagram of a bit counting $($counts number of $1$ s in input IN$1)$ digital circuit is shown below. It has one $32-$bit input IN$1$ and one control input Go$.$ There is a $6-$bit output bit$\_$count and a $1-$bit output done. The Go input is activated to start the process of bit counting. The output done indicates that bit counting is completed and the result is available on bit$\_$count output. It must remain one for one complete clock cycle. After bit counting is completed the circuit should go back to the initial state and wait for Go input. For example, if INI$=1000$FFF$0$H$,$ the result will be bit$\_$count $=13(001101).$ That is the number of $1$ s in $32-$ bit binary equivalent of hexadecimal value $1000$FFF bar$(0)$H$.$ You can use any method or algorithm you want to implement this digital circuit. Create an ASM chart that describes the operation of this digital circuit. Design the optimized datapath and control unit for this digital circuit $($minimize hardware and number of states used$).$ Use one$-$hot encoding for the control unit design. Show all the essential design details. Assume that all the commonly used combinational and sequential digital building blocks are available.

Hints:

To ensure that your ASM chart is correct verify it using simple test data

$$ e$.$g$.$ IN$1=0000003$DH$.$ In this case bit$\_$count $=5(000101)$

Bit counting can be done using shifting and counting, please show all steps