3. (20 pts) Measurements have shown that for an unpipelined machine A, the instruction mix and the average Clock cycle Per Instruction (CPID are as shown in the following table. OperationFrequency CP ALU instruction Load/Store Branch | 40% 40% 20% a) One improvement on the memory system can reduce the CPI for loads and stores to 3. This improvement, however, leads to a 20% increase in the clock cycle time. Is this improvement useful? Justify your answer quantitatively b) Another improvement makes the machine A to be pipelined. But, pipelining the machine addsa 10% overhead to the clock. Ignoring any latency impact, how much speedup in the instruction execution rate will be gained from a pipeline