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3 . 3 DATAPATH DESIGN For the successful operation of a 4 - bit Smart Climate Control system, the Datapath needs specific logic components such

3.3 DATAPATH DESIGN
For the successful operation of a 4-bit Smart Climate Control system, the Datapath needs specific logic
components such as a 2-to-4 Line decoder, four 1-bit AND gates, six 4-bit 2-to-1 Multiplexers, five 4-bit
registers, two 4-bit 4-to-1 Multiplexers, and a 4-bit Control and Calculation Unit (CCU) illustrated in Figure 1.
Figure 1: SCCS FSM & Datapath
Every logic block in the Datapath needs to be individually designed and simulated before being integrated
into the top-level design. The connections between each logic block must be established in the top-level design,
SCCS_DATAPATH, using a hierarchical design approach.
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You are required to develop parameterized Verilog code to define your Datapath. The CLK and other
control signals should come from the FSM.
The FSM control signals and Datapath operations:
wrt_addr signal provides an address to activate the required register as stated in Table 1.
Table 1: 2-to-4 Decoder Operation.
wrt_addr Registers
A B REG_3 REG_2 REG_1 REG_0
000001
010010
100100
111000
Toggle_TH is used to switch between temperature and humidity settings.
The wrt_en signal collaborates with wrt_addr and Toggle_TH to choose either a new value or retain
the previous value of Temperature/Humidity.
Input_sel is used to select either the Sensor value or the User-defined value. (Please note that in our
4-bit datapath, these values range between 0 and 15).
The load_data signal selects either the output of the input selection mux or the CCU output result.
The rd_addr1 and rd_addr2 signals specify the register addresses necessary for executing the CCU
operation between two registers using the provided ccu_opcode. The CCU must be designed to perform
the operations outlined in Table 2. You can use the behavioural approach to design the CCU.
Table 2: CCU Opcodes and Instructions.
alu_opcode Opr 1 Opr 2 Op Instruction
000---- noop ----
001 xx -- set R[xx]=1
010 xx -- increment R[xx]= R[xx]+1
011 xx -- decrement R[xx]= R[xx]-1
100 xx -- load R[xx]= Data_in
101 xx -- store Data_out = R[xx]
110 xx yy compare R[xx]= C(R[xx],R[yy])
111 xx yy copy R[xx]= R[yy]
*** Please note that these signals must be used in Datapath testbench to test all possible conditions required to
perform operations for SCCS.
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3.4 FSM DESIGN
The control unit for this Datapath will be managed by the SCCS_FSM, which comprises two main
subcomponents: FSM and FSM_DECO.
The SCCS_FSM will be equipped with seven external inputs: START, TOGGLE, 3 LED Flags
(indicating the Sensor and User value comparison result), CLK, RESET and one output DONE to indicate
that the operation is complete. The FSM takes these inputs and carries out all necessary control functions and
generates three outputs: opcode, operand1, and operand2.
The FSM_DECO will then utilize these three outputs for decoding, following the guidelines outlined in
Table 3. The FSM_DECO's output will be key in steering the Smart Climate Control system via the Datapath,
as illustrated in Figure 2.
Table 3: FSM_DECO Operations.
Op op_code Opr1 Opr2 ALU Rd_addr1 Rd_addr2 wrt_addr wrt_en load_data Input_sel
noop 000----000------0--
set 001 xx --001---- xx 10-
inc 010 xx --010 xx -- xx 10-
dec 011 xx --011 xx -- xx 10-
load 100 xx --100---- xx 111 or 0
store 101 xx --101 xx ----0--
compare 110 xx yy 110 xx yy xx 10-
copy 111 xx yy 111 yy -- Xx 10-
Figure 2: SCCS Hardware Algori

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