. . . 3. (3 points - Completeness) Pipeline. We have a pipelined warioCPU with the following nine stages (F1, F2, D, X1, X2, M1, M2, M3, WB), with a branch predictor and a branch target buffer (BTB). Assume the following: (see below for the explanation of how this works) Value loaded from Data Memory is ready at the end of M3. Branches are resolved at the end of X2 stage. Branch predictor achieves 85% accuracy BTB misses 10% of accesses for branches. Assume 50% of the branches are 'taken' branches. BTB also stores jumps and jump targets. For jumps, BTB misses 20% of the time. Jumps are resolved in the Decode stage D, in case of a BTB miss. BTB is accessed in the F1 stage. Given the following workload description, calculate the CPI when this workload runs on the given processor. 25% of instructions are branches (beq, bne, etc). 10% are unconditional branches (jumps). 40% are ALU operations (add, addi, sub, etc). 25% of instructions are lw. 30% of the instructions immediately following those loads (lw), are R-type and have a dependency on the load. i.e. They use the loaded register, in the Execute stages. No other data dependencies exist in the entire workload. 0 . . . . 3. (3 points - Completeness) Pipeline. We have a pipelined warioCPU with the following nine stages (F1, F2, D, X1, X2, M1, M2, M3, WB), with a branch predictor and a branch target buffer (BTB). Assume the following: (see below for the explanation of how this works) Value loaded from Data Memory is ready at the end of M3. Branches are resolved at the end of X2 stage. Branch predictor achieves 85% accuracy BTB misses 10% of accesses for branches. Assume 50% of the branches are 'taken' branches. BTB also stores jumps and jump targets. For jumps, BTB misses 20% of the time. Jumps are resolved in the Decode stage D, in case of a BTB miss. BTB is accessed in the F1 stage. Given the following workload description, calculate the CPI when this workload runs on the given processor. 25% of instructions are branches (beq, bne, etc). 10% are unconditional branches (jumps). 40% are ALU operations (add, addi, sub, etc). 25% of instructions are lw. 30% of the instructions immediately following those loads (lw), are R-type and have a dependency on the load. i.e. They use the loaded register, in the Execute stages. No other data dependencies exist in the entire workload. 0