Answered step by step
Verified Expert Solution
Question
1 Approved Answer
3. Consider the following assembly code: Instruction Description LOAD RI, MI Read data from memory address MI and store in RI. XOR R2, RI, RI
3. Consider the following assembly code: Instruction Description LOAD RI, MI Read data from memory address MI and store in RI. XOR R2, RI, RI Logical Ex-OR between contents of RI with RI and store result in R2 BNEZ R2, Target! Jump to Target if R2 is non-Zero ADD R7, RI, R5 Add contents of R1 and R5 and store to R7 AND R2, R7, R7 Logical Ex-OR between contents of R7 with R7 and store result in R2 Targetl: BEZ R2, Target2 Jump to Target if R2 is Zero LOAD R3, M2 LOAD R4, M3 ADD RIO, R3, R4 Target2: ADD R10, R3, R4 STORE M4, RIO Save contents of R10 to memory address M4 END Use five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Use the following format: Instructions /Time-step 12345 LOAD RI, MI XOR R2, RI, RI BNEZ R2, Target! ADD R7, R1, R5 XOR R2, R7, R7 Targetl: BEZ R2, Target2 LOAD R3, M2 LOAD R4, M3 ADD R10, R3, R4 Target2: ADD R10, R3, R4 STORE M4, RIO END Calculate the execution time. Assume that a multi-port RAM is used with the CPU running at 3GHz and each section requires 2 clock cycles
Step by Step Solution
There are 3 Steps involved in it
Step: 1
Get Instant Access to Expert-Tailored Solutions
See step-by-step solutions with expert insights and AI powered tools for academic success
Step: 2
Step: 3
Ace Your Homework with AI
Get the answers you need in no time with our AI-driven, step-by-step assistance
Get Started