3. Consider the following memory addresses:

3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253

a. Assume the CPU has a cache consisting of 16 blocks, each one storing 1 word. Assuming the cache is initially empty, identify the index given to each address by a direct-mapped caching approach, and state whether each access is a cache hit or a miss.

b. Repeat the previous exercise, but with a cache consisting of 8 blocks, each storing 2 words.

c. Repeat the previous exercise, but this time with a 2 levels cache, where L1 consists of 2 blocks with 4 words each, and L2 consists 4 blocks with 4 words each.

d. Suppose you have cache with a total of 8 words of storage. Which cache design would yield better performance (in terms of hits and misses) with these accesses: 1 word blocks, 2 word blocks, or 4 word blocks?