3. Consider the following MIPS program is to be run on a MIPS pipeline processor of form IF- ID-EX-MEM-WB lw $t5, 50($t3) lw $t3, 20($t5) sit $t3,$t3,$t5 sw $t3 ,20($t5) add $t2, $t1,$t2 Also, assume that in the event of an exception, the instructions to be evoked begin like this: 40000040hex sw $20, 1000($sl) 40000044hex sw $22, 1004($sl) (i) Examine how data dependences affect execution in the basic 5-stage pipeline. Draw the pipeline diagram, assume there is full forwarding. Indicate hazards and add NOP instructions to eliminate them. (4marks) (ii) Is there any load use hazard in the given code? If so, how will you reduce the stalls? Depict the diagram to eliminate the stall. (3marks) (iii) What happens in the pipeline if an overflow exception occurs in the add instruction? Identify the clock cycle at which the exception will be taken into the pipeline.(3marks)