3

Design a FSM that outputs 1 for consecutive 1 inputs and 0 otherwise. Think it accepts 1 bit at each time interval.

Example 1 Example 2

Input 00011010111 01101011101

Output 00001000011 00100001100

V Make the state diagram for MOORE DESIGN!

W Give state transition and encoded transition tables.

X Give mathematical equations for the output and the next state.

Y Think your system is working with a clock of 1 kHz, give timing diagram for sequence: 0011010101110. Please Show all critical time points for the Clock, Input, Output.

Z Give the Verilog code for the design.