3. Determine and explain why the following statement is true or false. 30% (a) Predicting "taken" for the backward branches is good. (b) The OS should clear all "dirty bits" to zero periodically. (c) Pipelining can reduce instruction latency because of parallel processing. (d) To apply LRU, we need to record the "reference bit". (e) Page table is implemented with SRAM. (f) TLB is greater than a typical cache