3. Superscalar Processors Given the superscalar processor in Figure 4.69 from the textbook, what is the maximum speedup it can achieve over the pipeline from Figure 4.65 for any MIPS program? You should assume that the superscalar pipeline is a static two-issue (i.e., a program places two instructions together that can propagate through the pipeline together without error) and has hardware stalling and forwarding equivalent to that of the scalar processor. Provide a MIPS program that executes at least 20 dynamic instructions that can achieve the maximum speedup without any correctness issues. Provide another MIPS program that executes 10 dynamic instructions on the scalar processor, but can't achieve any speedup once it is modified to run on the static two-issue processor. Turn in both versions of the program.

Figure 4.69:

Figure 4.65 :

4 Registers MI u PC Instruction 80000180 x | L | memory Write data Data ALUm Sign- xtend Sign- memory Address FIGURE 4.69 A static two-issue datapath. The additions needed for double issue are highlighted: another 32 bits from instruction 4 Registers MI u PC Instruction 80000180 x | L | memory Write data Data ALUm Sign- xtend Sign- memory Address FIGURE 4.69 A static two-issue datapath. The additions needed for double issue are highlighted: another 32 bits from instruction