3. The implementation of register forwarding in pipelined CPUs may increase the clock cycle time. Assume the clock cycle time is () 250ps if we do not implement register forwarding at all, (ii) 290ps if we only implement the EX/MEM.register-to-ID/EX.register forwarding (i.e., the case #1 shown on slide 12 in lecture note Session 12.pdf), and (iii) 300ps if implement the full register forwarding (i.e., both EX/MEM.register-to-ID/EX.register and MEM/WB.register-to-ID/EX.register forwarding). Given the following instruction sequence: or r1,r2,r3 or r2,r1,r4 or r1,r1,r2 a) Assume there is no forwarding in this pipelined processor. Indicate hazards and add nop instructions to eliminate them. them full forwarding? What is the speedup achieved by adding full forwarding to a pipeline b) Assume there is full forwarding. Indicate hazards and add nop instructions to eliminate c) What is the total execution time of this instruction sequence without forwarding and with that had no forwarding? ID/EX.register forwarding only. to-ID/EX.register forwarding? What is the speedup over a no-forwarding pipeline? d) Add nop instructions to this code to eliminate hazards if there is EX/MEM.register-to- e) What is the total execution time of this instruction sequence with only EX/MEM.register