3: (using Verilog array instantiation) Sketch the fbd of the module described by the Verilog code (that uses the Verilog array construct) below. module array_adder_v4 ( input Ci, input [3:0] a, b, output [4:0] sum ): wire [4:0] C; integerk, always @ (a, b, ci) begin C[O] = Ci: for (k=0; k