3. Using Verilog HDL data flow modeling design a 16-bit arithemtic unit as shown in the figure below. The unit has input control lines to select the required operation, two inputs (A and B) each with size of 16-bit and an output Y with size of 16-bit. Operation Description Control Input Opcode) 16 Y = Avg (A,B) Y = Min (A,B) Opcode Average value of two operands Minimum value of two operands Maximum value of two operands A modulo B Y = Max (A,B) Arithmetic Unit + 16 3 Y= A mod B 4. Write a test bench and use Modelsim to verify the functionality of the ALU in question 3