3. You are given the following MIPS-like code, which is executed in the MIPS 5-stage pipeline. li $0, 5 li $1, 1 li $2,1 li $3, 1 loop1: add $1, $1, $2 loop2: add $2, $1, $2 addi $0, $0, -1 slt $4, $0, $3 beq $4, $zero, loop1 Branches are assumed to be taken, and branch decisions and branch target computations are made in the ID stage. There are no delay slots. How many clock cycles are required to execute instructions in loop1, prior to starting loop2 (including all iterations of the loop and any control stalls)? Assume there are no data dependencies or structural hazards. a. How many control stalls are there? What is the branch prediction accuracy in percentage? b. rewrite the code to take advantage of this delay slot, and achieve the same output. How many clock cycles are required to complete loop1?