(30pts.) A 2 GHz pipelined processor implemented in 22nm process technology has an ideal CPU CPI of 1 when there are no misses at the first level of the memory hierarchy. On-die first level (L1) consists of a split (Instruction and Data) cache, while the on-die second level (L2) is unified. 30% of all instructions are of load/store type. The cache specifications are provided below. Local Access Time Level Properties (Local Hit Time) 32 kB, 4-way Set Associative Write-Back L1 Instruction Cache IL1 300 ps wih 14% miss rate, and 16 B block size 64 kB, 4-way Set Associative Write-Back L1 Data Cache wih 500 ps 20% miss rate, and 16 B block size 4 MB, 8-way Set Associative Write-Back L2 Unified Cache wih UL2 10 ns 32 B block size DL1 The byte-addressable main memory size is 16 GB, and access time is 200 ns. It can be assumed that all instructions and data can be found in the main memory. a) (8 pts.) i. State the advantage and disadvantage of the Write-Back policy for writing cache blocks. ii. Is a write buffer more performance-critical for write-back or write-through policy? Explain. b) (8 pts.) What is the maxiumum global miss rate that can be tolerated for UL2 cache (in %) if an assembly program with 1,000,000 instructions has to be executed in 5 ms? What is the local miss rate of UL2 under this condition? c) (8 pts.) What is the total number of SRAM bits you need to use for the implementation of the provided UL2, given the cache line status bits are V (valid), D (dirty), and 2 bits reserved to implement LRU block placement policy. d) (6 pts.) Based on evaluation of some new benchmarks, your team-mate has informed you that it will be impossible to satisfy the UL2 miss rate requirement from part (b). You have decided to re- design the second level of the cache hierarchy for the upcoming 13 nm process technology. List 3 architectural design enhancements you will investigate to reduce the miss rate in the second level