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* * * 4 . 1 7 In this problem we perform five successive accesses to memory. The following table shows for each access whether

***4.17 In this problem we perform five successive accesses to memory. The following table shows for each access whether it is a read (load) or write (store), and the contents of the MAR and MDR at the completion of the access. Some entries are not shown. Note that we have shortened the addressability to 5 bits, rather than the 16 bits that we are used to in the LC-3, in order to decrease the excess writing you would have to do.
\table[[Operation 1,Operations on Memory],[RW,MAR,,,?bar(ID),,],[W,,1,1,1,1,0],[Operation 2,,,,,,,],[Operation 3,W,,1,0,,,],[Operation 4,,,,,,,],[Operation 5,,,,,,,]]
The following three tables show the contents of memory locations x4000 to 4004 before the first access, after the third access, and after the fifth access. Again, not all entries are shown. We have added an unusual constraint to this problem in order to get one correct answer. The MDR can ONLY be loaded from memory as a result of a load (read) access.
Your job: Fill in the missing entries.
Hint: As you know, writes to memory require MAR to be loaded with the memory address and MDR to loaded with the data to be written (stored). The data in the MDR must come from a previous read (load).
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