4. 1 pt] Suppose an enable input is added to the 3-to-8 decoder from prelab problem 3. The enable input operates in the following manner: if enable', then the decoder will operate normally, otherwise, if enable 0', then all outputs will be '0'. How must you change your VHDL code in order to correctly add and implement this enable signal? Please explain (you do not need to write the new VHDL code Hint: You may want to revisit the lecture slides on std_logic_vectors to see how you can manipulate bits 4. 1 pt] Suppose an enable input is added to the 3-to-8 decoder from prelab problem 3. The enable input operates in the following manner: if enable', then the decoder will operate normally, otherwise, if enable 0', then all outputs will be '0'. How must you change your VHDL code in order to correctly add and implement this enable signal? Please explain (you do not need to write the new VHDL code Hint: You may want to revisit the lecture slides on std_logic_vectors to see how you can manipulate bits