4. [16 points (g-h are extra credit)] Suppose the following instruction is fetched by a processor with a single-cycle datapath such as the one shown in Figure 4.24 on page 271 in Patterson and Hennessy 1010 1100 0110 0010 0000 0000 0001 0100 The data memory is all Os and the registers contain the following values at the beginning of the cycle PC ac620014 r12 31 16 r0 rl r2 r3 r4 r5 10 r6 r8 Convert to MIPS format. What format instruction is used? What is the output of the sign-extend unit (near the bottom of figure 4.24) for this instruction word? What are the values of the ALUOp and ALUSrc for this instruction? Briefly explain the purpose of the mux just to the left of the ALU? (Use the lower ALU marked ALU) a. b. c. d. e. What is the new PC after this instruction is executed f. What is the output of the Mux that provides an input to the ALU. (The one controlled by ALUStC)? What are the inputs for the ALU? What are the inputs for the two Add units? g. h. 4. [16 points (g-h are extra credit)] Suppose the following instruction is fetched by a processor with a single-cycle datapath such as the one shown in Figure 4.24 on page 271 in Patterson and Hennessy 1010 1100 0110 0010 0000 0000 0001 0100 The data memory is all Os and the registers contain the following values at the beginning of the cycle PC ac620014 r12 31 16 r0 rl r2 r3 r4 r5 10 r6 r8 Convert to MIPS format. What format instruction is used? What is the output of the sign-extend unit (near the bottom of figure 4.24) for this instruction word? What are the values of the ALUOp and ALUSrc for this instruction? Briefly explain the purpose of the mux just to the left of the ALU? (Use the lower ALU marked ALU) a. b. c. d. e. What is the new PC after this instruction is executed f. What is the output of the Mux that provides an input to the ALU. (The one controlled by ALUStC)? What are the inputs for the ALU? What are the inputs for the two Add units? g. h