$4.(30\text{'})$ Verilog design of sequential circuit: The block diagram and state transition graph of a sequence detector is shown in Figure $4.$

$(1).$ Is it Mealy machine or Moore machine? How do you know? Assume initial state is A$,$ based on STG$,$ can you guess what sequence $($four$-$bit$)$ this circuit detects? $($Hint: follow the "lucky$-$day" input sequence in STG to achieve output $z=1)$

$(2).$ Use the template we learned in the class, can you write Verilog code $($STG$-$based$)$ to design this sequential circuit?

$(3).$ Use the template we learned in the class, can you write Verilog testbench file to test this sequential circuit? Use the last digit of your student ID and convert it into four$-$bit binary sequence for testing. For example, if the last digit of your student ID is $"9"="{1001}_2",$ then you can set your test pattern as $x=1$longrightarrowO$O1$ as your test pattern sequence. Each test pattern lasts for $10ns.$

$($a$)$

$($b$)$

Figure $4.$ A sequence detector circuit $($Mealy machine$)($a$).$ block diagram $($b$).$ State transition graph