4. (30%) We will be implementing a new instruction within the MIPS architecture. It will be used to clear data (write all O's) into a memory location addressed by Offset+registercontent, WHILE Unconditionally branching to a new Branch location using lower 16 bits. It will be called CLBRA : Clear and Branch Always. Usage: CLBRA Rs(Rd), BranchLoc Interpretation: Mem[Rd+Rs] = 0, PC= BranchLoc station: MemiliBed 3RCRE), Because Which blocks are used and which control signals are generated for this instruction. How would the Instruction code fields look like? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow) 4. (30%) We will be implementing a new instruction within the MIPS architecture. It will be used to clear data (write all O's) into a memory location addressed by Offset+registercontent, WHILE Unconditionally branching to a new Branch location using lower 16 bits. It will be called CLBRA : Clear and Branch Always. Usage: CLBRA Rs(Rd), BranchLoc Interpretation: Mem[Rd+Rs] = 0, PC= BranchLoc station: MemiliBed 3RCRE), Because Which blocks are used and which control signals are generated for this instruction. How would the Instruction code fields look like? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow)