4. (5 points, With 1 or more errors you get 0 points. Otherwise full point.) Consider a three level memory: L1 and L2 are for cache memory and the third level is for the main memory. Access time for L1 is 1 clock cycle, the access time for L2 is two times more than L1 and main memory access time is 10 times more than L2. The miss rate for L1 is 20% and the miss rate for L2 is 5%. What is the effective clock cycle for memory access (AMAT in number of clock cycles)? With 2 GHz clock rate how much time is needed for a program with 1012 instructions to execute