4 and 5 pls

ty for helping!

4. (20 points) (Cache) Assume we have a 64 -bit machine. The machine has 32KBL11 cache, 32KB K L1 D-cache, and 128KBL2 unified cache. The block size of L11-cache, L1 D-cache, and L2 unified cache are 32B, 64B, and 128B, respectively. Please answer the following questions. (a) (6 pts) For the L1 1-cache, what is the number of index bits when it is organized as a direct-mapped cache? (b) (6 pts) For the L1 D-cache, what is the number of tag bits when the cache is two-way set-associative? (c) (8 pts) For the 4-way set-associative L2 unified cache, given memory address OxAABBFFOOEE22CC44, which set is the address mapped to? What is the tag field of the address? 5. (24 points) (Virtual Memories) Assume we have a 64-bit machine, and the page size is set to 8KB. Assume the physical main memory has 32GB capacity. Please answer the following questions. (a) (4 pts) What is the virtual page number? $ th f bit (b) (4 pts) What is the physical page number? H it hit (c) (8 pts) A conventional page table has one entry for each virtual page, and each entry has 1-bit field for storing valid bit, and a field for storing the physical page number that the virtual page is mapped to. What is the total number of bits of the page table? (d) (8 pts) What is a translation look-aside buffer (TLB) for? What will happen during L1 cache accesses if a CPU has no TLB