4 bit tree adder in verilog

I am trying to make a four bit tree adder. I think the following code is correct, but how do I go from Gs and Ps to a sum? Are G and P the two numbers being added? Or should they somehow be generated from 2 four bit inputs like they are in a look ahead addder with a carry chain?

module treetopfr (g,p,cin,gout,pout,cout); input [7:0]g,p; input [3:0]cin; output [3:0] gout,pout; output [7:0]cout; wire [3:0]cw,gw,pw;

treetop (g[7:4],p[7:4],cw,gw,pw,cout[7:4]); treetop (g[3:0],p[3:0],cin,gout,pout,cout[3:0]); treetop (gw,pw,cin,gout,pout,cw); endmodule //__________________________________________________________________ module treetop (g,p,cin,gout,pout,cout); input [3:0]g,p; input [1:0]cin; output [1:0] gout,pout; output [3:0]cout; wire [1:0]cw,gw,pw;

treeElement (g[3:2],p[3:2],cw[1],gw[1],pw[1],cout[3:2]); treeElement (g[1:0],p[1:0],cw[0],gw[0],pw[0],cout[1:0]); treeElement (gw,pw,cin,gout,pout,cw); endmodule //__________________________________________________________________ module treeElement (g,p,cin,gout,pout,cout); input [1:0]g,p; input cin; output gout,pout; output [1:0]cout;

assign cout[1]=g[1]|p[1]&cout[0]; assign cout[0]=cin; assign gout=g[1]|g[0]&p[0]; assign pout=p[1]&p[0]; endmodule

Adder sum gp DO 9 SS SS Tutti 11. JUAJI 111 111 LAC LAC LAC LAC LAC LAC 111 111 111111 LAC TUT GP Cin Each LAC is the copy of the following cl=g1+p1 co co=cin gout=g1+go po pout=pl po gl pl cl gO pO c0 LAC gout pout cin