(1) Translation Lookaside Buffer (TLB) can be considered as a cache of Page Table Entries (PTE), where each cache block is just a single page table entry. Consider there is a 32-bit single-core CPU with a 128 entry fully-associative TLB. Each memory page is 4KB. Consider that both the virtual memory address and physical memory address are 32 bits.

Please answer the following questions.

1. During the address translation, how many bits are used for offset inside a page?

2. How many bits are used for indexing different sets?

3. How many bits are used for the tag?

4. Consider there is an application that uses 200 MB physical memory. How many page table entries are needed by this application? Can all these entries be cached in the TLB?