4. Design an event driven sequence detector which produces a 1 at its output z in response to the input sequence X2X1 = {11,01,00}. It may be assumed that the inputs X2 X1 cannot change simultaneously. In the design procedure show: (a) the state diagram; [8 mark] (b) the complete and merged state tables; [6 marks] (c) the race free state diagram; [4 marks] (d) the turn on/off set equations; [4 marks] (e) a block diagram of the circuit implementation using NAND gates only; [4 maks] (f) f a block diagram of the circuit implementation using SR flip-flops and NAND gates only. [4 marks]