4. For a direct-mapped design with a 32-bit address,the following bits of the address are used to access he cache Tag 31-15 Index 14-5 Offset 4-0 What the cache line (block) size (in words)? a. b. How many entries does the cache have? What is the ratio between total bits required for such a cache implementation over the data storage bits? c. 5. Using the series of references given in Question #1, show the hits and misses and final cache contents for a two-way set associative cache with one word block and a total size of 16 words. Assume LRU replacement. What is the hit rate of the cache? Set Block Valid H bit Reference Hit or miss Tag Data 4 20 17 19 4 4 17 31 Hit rate