4. Scheduling Instruction in the MIPS Pipeline. You have a standard 5-stage MIPS pipeline and the following code segment: [20 pts] sub $t1, $t2, $t1 and $t2, $tl, $t3 or $t3, $tl, $t2 sub $t2, $t2, $t3 or $t3, $tl, $t2 If forwarding (and stalls) are available, schedule the code in the pipeline using the diagrams below. Clearly label the instruction that is in the pipeline, stall cycles (if any), and what register is forwarded at which stage. Stalls can be indicated by Xs in the stages. Note: You may not need all of the stages provided below. a. b. How many clock cycles does it take to execute the code fragment with forwarding and stalls? If there is no forwarding available (only stalls), how many clock cycles does it take to execute the code? c