4. Suppose we have 220 bytes of virtual memory and 26 bytes of physical main memory. Suppose the page size is 28 bytes. a. How many pages are there in the virtual memory? b. How many page frames are there in the main memory? c. How many entries are in the page table for a process that uses all of the virtual memory? 5. For the system in problem 4, suppose a main memory access requires 30ns, the page fault rate is .01%, and it costs 12ms to access a page, not in memory (this time includes the time necessary to transfer the page into memory, update the page table, and access the data). Also, suppose a TLB hit requires 7ns, the cache miss rate is 3%, the TLB hit rate is 95%, and a cache hit requires 15 ns. On a TLB or cache miss, the time needed for access includes a TLB and cache update, but the access is not restarted. On a page fault, the page is fetched from the disk, and all updates are performed, but the access is restarted. All references are sequential (no overlap, nothing done in parallel). a. Calculate the time for a TLB hit and a cache hit. b. Calculate the EAT (effective access time) for a TLB hit.