4. The following figure illustrates the forwarding circuit in the 5 -stage pipeline. Please explain how it works and give two examples (MIPS codes) to demonstrate why such a scheme can reduce data stall(s) in a pipeline. 15% 5. For a direct-mapped cache design with 32-bit address, the address bit distribution is as follows. Tag: bit 31-14, Index: bit 13-6, offset: bit 5-0. (a) What is the block size (in words)? How many entries does this cache have? What is the ratio between total bits required for such a cache implementation over the data storage bits? 10% (b) Starting from power on, the following byte-addressed references are recorded: 0,4,16,132,232,160,1024,30,140,3100,180,2180. How many blocks are replaced? What is the hit-ratio? List the final state of the cache, with each valid entry represented as a record of [index, tag, data]. 20%