4. TLB (8 points - Correctness): Mario's TLB is 2-way set associative and holds 8 translations. It has the following entries. Virtual memory addresses consist of 32 bits with a 12 bit page offset. The virtual page number tag in the TLB excludes the 2 bit index and therefore is 18 bits. The 18 bit tag is shown in the TLB table below in the form: {top 16 bits in hex (0XXXXX), bottom 2 bits (bXX) in binary} The physical page number consists of 28 bits. Index Virtual Page #Tag Physical Page # Tag vill Virtual Page #Tag Physical Page #Tag 0 {0x4227, b10} Ox1234567 {0x5CDD, 601} Ox7642867 1 {Ox0000, 600} Ox345df44 {OxA667, b10} 0x2345647 2 {OXCCD3, 601} OxDBD234D {0x1265, b10} 0x234BDCE 3 3 {OxF23F, 601} OxAB578BC {0x6D90, b11} Ox0187109 (a) Fill out the two rightmost columns of the memory access table below to denote whether the memory access was a hit or a miss in the TLB. The cache uses an LRU replacement policy, and you may assume that to start with, the right entry is the least recently used. When there is a miss, indicate which set, and which column (or way) (left or right) is replaced or filled. Virtual Mem Access Result (Physical Mem Hit/Miss Evicted Set/column Address) 0x42278000 Ox1234567000 Ox00001077 0x345DF44077 Ox8703C12E 0x764286712E Ox5CDD4AD2 0x7642867AD2 Ox339541DO OxDB32D781DO OxBEEDDO20 0x3092834020 OxA667B9DC 0x23456479DC OxCCD35293 OxDBD234D293 (b) What are the contents of the TLB after processing the page accesses from (a)? Index Virt Page # Tag Phys Page # Tag Virt Page # Tag Phys Page # Tag 0 1 2. 3