4.12 Examine the difficulty of adding a proposed swap rs1, rs2 instruction to RISC-V. Interpretation: Reg[rs2]=Reg[rs1]; Reg[rs1]=Reg[rs2]

4.12.1 [5] <4.4> Which new functional blocks (if any) do we need for this instruction?

4.12.2 [10] <4.4> Which existing functional blocks (if any) require modification?

4.12.3 [5] <4.4> What new data paths do we need (if any) to support this instruction?

4.12.4 [5] <4.4> What new signals do we need (if any) from the control unit to support this instruction?

4.12.5 [5] <4.4> Modify Figure 4.21 to demonstrate an implementation of this new instruction.