4.25 Consider the following loop.

LOOP: LDUR X10, [X1, #0] LDUR X11, [X1, #8] ADD X12, X10, X11 SUBI X1, X1, #16 CBNZ X12, LOOP

Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, that the pipeline has full forwarding support, and that branches are resolved in the EX (as opposed to the ID) stage.

4.25.1 [10] <4.7> Show a pipeline execution diagram for the first two iterations of this loop. 4.25.2 [10] <4.7> Mark pipeline stages that do not perform useful work. How often while the pipeline is full do we have a cycle in which all five pipeline stages are doing useful work? (Begin with the cycle during which the SUBI is in the IF stage. End with the cycle during which the CBNZ is in the IF stage.) Only answer question 4.25.2. Thank you!