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4.5 In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock
4.5 In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 0xf8014062
4.5.4 [10] For each mux, show the values of its input and outputs during the execution of this instruction. List values that are register outputs at Reg [Xn].
4.5.5 [10] What are the input values for the ALU and the two add units?
ANSWER longer offset but it is not conditIO branch address are always 00 from the 26-bit immediate field in the instruction Thus, we can implement a branch by storing into the PC sum o theex sign extended and shifted 26-bit offset. Figure 4.23 shows the addiand control for branch added to Figure 4.17. An additional OR-gate isn op control signal to select the branch target PC always. This control sig and sum ot addition of hesis used with The next 26 B then are the register is 1 (see C likely to b The pe but migh compute Howeve more C condBranch, is asserted only when the instruction is an unconditional Bec Add for all delay Add result Reg2Loc Uncondbranch Shift left 2 con Instruction [31-211 Control MemRead Control emtoR PiP RegWrite ef PC-j address Instruction [9-5] Instruction [20-1register 1 Read Read data 1 Write data 2 Instruction Zero 31-0] xregister 2 ALU ALU-1 Address' data -[ Instruction Instruction (4-0) Read1 memory register data 2 result MI LI Write data Registers Write Data l data memory Instruction [31-0] 32 Sign- 64 ALU control extend nstruction [31-21] FIGURE 4.23 The simple control and datapath are extended to handle the unconditional branch instruction. An additional OR-gate (at the upper right) is used to control the multiplexor that chooses between the branch target and the sequential instruction following this one. One input to the OR-gate is the Uncondbranch control signal. Although not shown, the Sign-extend logic would recognize the unconditional branch opcode and sign-extend the lower 26 bits of the branch instruction to form a 64-bit address to be added to the PC
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