5. Design a circuit to interface Intel 8086 microprocessor with 16kB RAM in maximum mode. Use the SRAM chip and the supporting chips as shown in Figure-2 for the interconnection. Also specify the address for each SRAM chip. [10] NC 2 A12 20 VCC 8Q 19 8D 18 3 A7 1Q-8Q are inputs 1D-8D are outputs 24 8886608 4364 SRAM 22 VCC 28 WE 27 CE2 26 A8 25 A9 A11 23 OE A10 20 19 I/O8 I/O7 18 I/O6 17 1/05 16 1/04 15 3 4 S 6 7 8 4D 9 4Q 10 GND 7012 70.16 6Q 15 4 A6 S A3 6 A4 7 A3 8 A2 9 A1 10 A0 11 I/O1 12 I/O2 13 1/03 GND 74373 LATCH Q=D FOC = 0 and C = 1 21 6D 14 SD 13 12 5Q 11 VCC B 3 16 YO 15 Yi 14 4 G2A SG2B CE1 and CE2: chip enable pins OE: Outpute enable(Read) WE: Write enable NC No connection A0-A12: Address pins 1/01-1/08 : Input/Output (data) pins 6 G1 Y2 13 Y3 12 Y411 YS 10 Y69 1147 G2A, G2B, G1 are enable pins A,B,C are inputs YO-Y7 are outputs active low) GND 74138 DECODER Activate Go to Setti Figure-2 5. Design a circuit to interface Intel 8086 microprocessor with 16kB RAM in maximum mode. Use the SRAM chip and the supporting chips as shown in Figure-2 for the interconnection. Also specify the address for each SRAM chip. [10] NC 2 A12 20 VCC 8Q 19 8D 18 3 A7 1Q-8Q are inputs 1D-8D are outputs 24 8886608 4364 SRAM 22 VCC 28 WE 27 CE2 26 A8 25 A9 A11 23 OE A10 20 19 I/O8 I/O7 18 I/O6 17 1/05 16 1/04 15 3 4 S 6 7 8 4D 9 4Q 10 GND 7012 70.16 6Q 15 4 A6 S A3 6 A4 7 A3 8 A2 9 A1 10 A0 11 I/O1 12 I/O2 13 1/03 GND 74373 LATCH Q=D FOC = 0 and C = 1 21 6D 14 SD 13 12 5Q 11 VCC B 3 16 YO 15 Yi 14 4 G2A SG2B CE1 and CE2: chip enable pins OE: Outpute enable(Read) WE: Write enable NC No connection A0-A12: Address pins 1/01-1/08 : Input/Output (data) pins 6 G1 Y2 13 Y3 12 Y411 YS 10 Y69 1147 G2A, G2B, G1 are enable pins A,B,C are inputs YO-Y7 are outputs active low) GND 74138 DECODER Activate Go to Setti Figure-2