5) For the given logic circuit, assume that all the gates are perfect gates (no timing delay), complete the waveform for w, x, y and z respectively. 6) For the given logic circuit, assume that all the gates are perfect gates (no timing delay), complete the waveform for w, x and y respectively. 5) For the given logic circuit, assume that all the gates are perfect gates (no timing delay), complete the waveform for w, x, y and z respectively. 6) For the given logic circuit, assume that all the gates are perfect gates (no timing delay), complete the waveform for w, x and y respectively