5. For this question you will answer questions about Verilog coding and timing diagrams module code output reg (1:0) out_510. input wire clk, input wire cir, ) a) Based on the code on the right, list the inputs and outputs below. Indicate any busses and the size of each bus found. always (posedge clk or posedge ciz) (car 1) out_sig = 0; else out_sig