5. Given the User Mode register and memory contents shown below, predict the register contents and, where appropriate, the flag states produced by each of the following ARM/XScale instructions. Assume the values shown for register and memory contents are all in hexadecimal, assume Little-Endian memory storage, and assume the instructions are not sequential. NA for flags not affected. RO 12345678 R1 FFFF0000 R2 - EOAB5023 R3-00000000 R4- 80000130 R5 -80000140 R8-0000003 R9 R10- R11- R12 R13 R14 PC(R15) R7- ADDRESS CONTENTS (INCREASING ADDRESSES from left to right) (hex) (hex) 80000130 04 77 59 27 99 22 14 53 80000138 FF 73 92 45 3A 33 2B 7A 80000140 27 98 42 70 CC 45 23 DF SCORES NZC R2 Flags a. ANDS R2, R2, R1 R1 Flags,- ;R0 R4_ b. LDR R0, [R4],#8 R1 Flags RO c. CMP R1, RO