5. Sketch the state transition diagram for the FSM described by the following SystemVerilog module. (15 points) module question5(input logic clk, reset, a, b, output logic q); typedef enum logic [1:0] [S0, S1, S2} statetype; statetype [1:0] state, nextstate; always ff @ (posedge clk, posedge reset) if (reset) state