5. Suppose you are running a program with the following data access pattern. The pattern is executed only once 0xO 0x8 0x10 Ox18 0x20 0x28 (a) I you use a direct mapped cache with a cache size of 1 KB and a block size of 8 bytes (2 words) many sets are in the cache (b) With the same cache and block size as in part (a), what is the miss rate of the direct mapped cache for the given memory access pattern? (c) For the given memory access pattern, which of the following would decrease the miss rate the most? (Cache capacity is kept constant.) Circle one. i. Increasing the degree of associativity to 2. ii. Increasing the block size to 16 bytes. i. Either () or (i). iv. Neither() nori) 2c12 8). Give your 6. You are building an instruction cache for an ARM processor. It has a total capacity of 4 C bytes (b bytes. It is N-2-way set associative (N 28), with a block size of b 2 answers to the following questions in terms of these parameters. (a) Which bits of the address are used to select a word within a block? (b) Which bits of the address are used to select the set within the cache? (c) How many bits arein each tag? (d) How many tag bits are in the entire cache? 7. Consider a cache with the following parameters: N (associativity)2, b (block size)2 words, W 32 K words, A (address size) 32 bits. You need consider only (word size) 32 bits, C (cache siz word addresses (a) Show the tag, set, block offset, and byte offset bits of the address. State how many bits are needed for each held (b) What is the size of all the cache tags in bits? (c) Suppose each cache block also has a valid bi V) and a dirty bit (d) What is the size of each cache set, including data, tag, and status bits? (e) Design the cache using the building blocks in Figr and a small number of two-input logic gates. The cache design must include tag storage, data storage, address comparison, data output selection, and any other parts you feel are relevant, Note that theltiplexer and comparator blocks may be any size (n or p bits wide, respectively), but the SRAM blocks must be 16K x 4 bits. Be sure to include a neatly labeled block diagram You need only design the cache for reads. 16K x4 Figure 1: HW 3 Problem 7