5. The pipelined MIPS processor is running the following program. Which registers are being written, and which are being read on the fifth cycle? addi $s1, $s2, 5 sub $to, $t1, $t2 lw $t3, 15($s1) sw $t5, 72($to) or $t2, $$4, $s5 6. Use the pipelined datapath diagram and show the forwarding needed to execute the following program with three instructions: 3 9 Time (cycles) add sto, sso, ss1.ip - EHEuEF DM sub $to, $to, $s2 and $t2, $t1, Sto