[50%] Consider the following stream of memory word addresses directed at the cache. Assume that the memory is word addressable, and the total cache capacity is 128 words. Further assume that the cache is 2-way set-associative, the cache line size is 16 words and the LRU replacement policy is used. 5, 6, 7, 1, 12, 2049, 2050, 2, 67, 74, 77,3, 208, 615, 1500, 45000 For each of these accesses, indicate whether it is a cache hit or a cache miss, show how you computed the cache index, and depict the contents of the cache after every access. You do not have to show the tag bits, only show the addresses of the cached data. [50%] Consider the following stream of memory word addresses directed at the cache. Assume that the memory is word addressable, and the total cache capacity is 128 words. Further assume that the cache is 2-way set-associative, the cache line size is 16 words and the LRU replacement policy is used. 5, 6, 7, 1, 12, 2049, 2050, 2, 67, 74, 77,3, 208, 615, 1500, 45000 For each of these accesses, indicate whether it is a cache hit or a cache miss, show how you computed the cache index, and depict the contents of the cache after every access. You do not have to show the tag bits, only show the addresses of the cached data